FIGS. 1 and 2 are a cross-sectional view and an equivalent circuit diagram, respectively, of a conventional DRAM (Dynamic Random Access Memory). A memory cell includes a p well 2 formed in a predetermined part of a silicon substrate 1 manufactured through a p-type impurity doping process, and a pair of field oxide films 4, having doping layers 3 therebeneath, are formed at a predetermined distance therebetween to distinguish an element isolation region from an active region. A plurality of word lines 6' are connected to switching transistors and a transfer transistor gate electrode 6 formed at a predetermined part of the active region and the element isolation region on the substrate.
A capacitor includes a storage node electrode 7, a dielectric film 8, and a plate electrode 9, being combined with the switching transistors having a lower insulating film 10 therebetween. A contact hole is formed through insulating films formed on the switching transistors to expose a region of the switching transistors. A bit line 11 is formed on the upper insulating film 10' having the contact hole to be coupled to the exposed region.
FIG. 2 shows the equivalent circuit diagram of the DRAM cell. When a data signal to be stored is applied to a corresponding bit line 11 while a voltage exceeding the threshold voltage of the transfer transistor gate electrode 6 is applied to the corresponding word line 6', the transistor is turned on. The data is stored as a charge in the capacitor of the cell. After storage, the voltage of the word line 6' is lowered to switch off the transfer transistor and the data signal charge does not escape. When the stored data signal is read, a voltage is applied to the corresponding word line 6' again and the charge accumulated in the cell capacitor (a) is transmitted through the bit line 11 to a sense amplifier connected thereto. Through the abovementioned course, writing and reading operations are performed.
The conventional DRAM cell is disadvantageous since the field oxide film 4 is formed having the P well 2 and the element isolation region on the silicon substrate 1 (for example, a field insulation doping layer), isolation of the elements is difficult. Further, because the switching transistor is formed only on the silicon substrate, a cell array takes up a larger area. Only one surface of the storage node electrode 7 serves as a capacitor (a), and the capacity of the capacitor per cell area is limited. The operational speed is also delayed in accordance with a contact resistance between the switching transistor and a connection (b shown in FIG. 1) for the storage node electrode 7. Moreover, data may be lost by a leakage current generated at the contact region of the storage node electrode 7.